In the field of molecular electronics, few materials show as much promise as carbon nanotubes that comprise hollow cylinders of graphite that have a diameter of a few Angstroms. Nanotubes can be implemented in electronic devices, such as, for example, diodes and transistors, depending on the nanotube characteristics. Nanotubes are unique for their size, shape and physical properties. For example, carbon based nanotubes resemble a hexagonal lattice of carbon rolled into a cylinder.
Besides exhibiting intriguing quantum behaviors even at room temperature, nanotubes exhibit at least two important characteristics; a nanotube can be either metallic or semiconducting depending on its chirality, i.e., conformational geometry. Metallic nanotubes can carry an extremely large current density with constant resistivity. Semiconducting nanotubes can be electrically switched “on” or “off” as field effect transistors (FETs). The two types may be covalently joined (i.e., sharing electrons). These characteristics point to nanotubes as excellent materials for making nanometer sized semiconductor circuits.
Carbon based nanotubes are thus becoming strategically important for post-scaling of conventional semiconductor technologies. For example, the inclusion of pFET devices within an nFET, CMOS, or BiCMOS process requires providing an n-well to place the pFET. A pFET device, like its nFET counterpart, is typically formed with a lateral source-body-drain arrangement. Drawbacks in such technologies include pFET device performance lagging the nFET due to lower mobility and separation requirements between the nFET and the pFET due to necessary well boundaries.
Additionally, SRAM cell pFET load devices have been formed in polysilicon layers over the SRAM nFET. However, pFET device performance and process complexities to form the polysilicon level to form the pFET are drawbacks in such logic devices.
In view of the drawbacks mentioned above with prior art semiconductor structures, there is a need to provide a hybrid semiconductor structure including a horizontal semiconductor device in which a vertical carbon nanotube transistor has been integrated therein improving the performance of the structure, while shrinking the overall size of the structure.